Kostas Pagiamtzis, Ph.D.
I consult in the area of semiconductor integrated circuit design, specifically in as technical and strategic advisor. I have extensive experience in modern/FinFET high-speed custom integrated circuit design. My particular interest is in advising in flow development (layout optimization, electromigration, aging), and in helping improve design efficiency and design velocity.
This website is mostly an archive of my pre-industry life, including my scholarly publications and a small number of articles that I have written on various topics. I received the Ph.D. degree from the Department of Electrical and Computer Engineering at the University of Toronto. I also received from the University of Toronto, the Bachelor of Applied Science (B.A.Sc.) degree from the Division of Engineering Science.
I was interviewed about my experience as a teaching assistant for an article in the Jobs section of Nature: Education: Time to teach. The interview came about because of the article I wrote called The Art of TAing, A Guide for Tutorial Teaching Assistants.
List of Articles and Pages
- Detailed List of Publications
- K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar 2006.
- K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, September 2004.
- K. Pagiamtzis, N. Azizi, and F.N. Najm, “A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme,” in IEEE Custom Integrated Circuits Conference (CICC), September 2006, pp. 301–304
- K. Pagiamtzis and A. Sheikholeslami, “Using cache to reduce power consumption in content-addressable memories (CAMs),” in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 369–372.
- H. Kimura, K. Pagiamtzis, A. Sheikholeslami and T. Hanyu, “A study of multiple-valued magnetoresistive RAM (MRAM) using binary MTJ devices,” in IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2004, pp. 340–345.
- K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in IEEE Custom Integrated Circuits Conference (CICC), September 2003, pp. 383–386.
- K. Pagiamtzis and P.G. Gulak, “Empirical performance prediction for IFFT/FFT cores for OFDM systems-on-a-chip,” in IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2002, vol. 1, pp. 583–586.