A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme

K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, September 2004.

Abstract

This paper presents two techniques to reduce power consumption in content-addressable memories (CAMs). The first technique is to pipeline the search operation by breaking the match-lines into several segments. Since most stored words fail to match in their first segments, the search operation is discontinued for subsequent segments, hence reducing power. The second technique is to broadcast small-swing search data on less capacitive global search-lines, and only amplify this signal to full swing on a shorter local search-line. As few match-line segments are active, few local search-lines will be enabled, again saving power. We have employed the proposed schemes in a 1024 x 144-bit ternary CAM in 1.8-V 0.18-μm CMOS, illustrating an overall power reduction of 60% compared to a nonpipelined, nonhierarchical architecture. The ternary CAM achieves a 7-ns search cycle time at 2.89 fJ/bit/search.

List of Citations of This Paper

  1. J.-S. Wang, H.-Y. Li, C.-C. Chen, C. Yeh, “An AND-type match-line scheme for energy-efficient content addressable memories,” in IEEE Solid-State Circuits Conference (ISSCC), February 2005, pp. 464–465, 610. [IEEE Xplore entry]

  2. K. Degawa, T. Aoki, H. Inokawa, T. Higuchi, and Y. Takahashi, “A two-bit-per-cell content-addressable memory using single-electron transistors,” in IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2005, pp. 32–38.
    [IEEE Xplore entry]

  3. B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1736–1744, August 2005.
    [IEEE Xplore entry]

  4. I. Arsovski and R. Nadkarni, “Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines,” in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 447–450.
    [IEEE Xplore entry]

  5. K. Pagiamtzis and A. Sheikholeslami, “Using cache to reduce power consumption in content-addressable memories (CAMs),” in IEEE Custom Integrated Circuits Conference (CICC), September 2005, pp. 369–372.

  6. P. Echeverría, J. L. Ayala, and M. López-Vallejo, “Practical implementation of a low-power content addressable memory,” in Design of Circuits and Integrated Systems Conference, November 2005.

  7. J.-S. Wang, C.-C. Wang and C. Yeh, “TCAM for IP-address lookup using tree-style AND-type match lines and segmented search lines,” in IEEE International Solid-State Circuits Conference (ISSCC), February 2006, pp. 166–167, 646.

  8. K. McLaughlin, N. O'Connor, S. Sezer, “Exploring CAM design for network processing using FPGA technology,” in Advanced International Conference on Telecommunications/International Conference on Internet and Web Applications and Services (AICT/ICIW), February 2006, pp. 84–88.
    [IEEE Xplore entry]

  9. K. Pagiamtzis and Ali Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712–727, March 2006.

  10. B. Agrawal and T. Sherwood, “Modeling TCAM Power for Next Generation Network Devices,” in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 120–129, March 2006.
    [IEEE Xplore entry]

  11. H. Qin and T. Sasao, “Design of address generators using multiple LUT cascade on FPGA,” in Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), April 2006, pp. 146–152.

  12. P. Echeverría, J.L. Ayala, M. López-Vallejo, “A low-power pipelined CAM for high-performance IP routing,” in IEEE International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), April 2006.

  13. H.-Y. Li, C.-C. Chen, J.-S. Wang, C. Yeh, “An AND-type match-line scheme for high-performance energy-efficient content addressable memories,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1108–1119, May 2006.
    [IEEE Xplore entry]

  14. T. Sasao and J.T. Butler, “Implementation of multiple-valued CAM functions by LUT cascades,” in IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2006.
    [IEEE Xplore entry]

  15. T. Sasao, “Design methods for multiple-valued input address generators,” in IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2006.
    [IEEE Xplore entry]

  16. N. Mohan, W. Fung, D. Wright, and M. Sachdev, “Match line sense amplifiers with positive feeedback for low-power content addressable memories” in IEEE Custom Integrated Circuits Conference (CICC), September 2006, pp. 297-300.

  17. C. Zhang, “A Low Power Highly Associative Cache for Embedded Systems,” in IEEE International Conference on Computer Design(ICCD), October 2006.

  18. L. Kothari and N.P. Carter, “Architecture of a self-checkpointing microprocessor that incorporates nanomagnetic devices,” IEEE Transactions on Computers, vol. 56, no. 2, pp. 161–173, February 2007.
    [IEEE Xplore entry]

  19. H. Nakahara, T. Sasao and M. Matsuura, “A CAM emulator using lookup-table cascades,” in Reconfigurable Architectures Workshop, March 2007.

List of References

  1. T.-B. Pei and C. Zukowski, “Putting routing tables in silicon,” IEEE Network Magazine, vol. 6, pp. 42–50, January 1992.
    [IEEE Xplore entry]

  2. L. Chisvin and R. J. Duckworth, “Content-addressable and associative memory: Alternatives to the ubiquitous RAM,” IEEE Computer, vol. 22,pp. 51–64, July 1989.
    [IEEE Xplore entry]

  3. H. Miyatake, M. Tanaka and Y. Mori, “A design for high-speed lowpower CMOS fully parallel content-addressable memory macros,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 956–968, June 2001.
    [IEEE Xplore entry]

  4. I. Arsovski, T. Chandler and A. Sheikholeslami, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 155–158, January 2003.
    [IEEE Xplore entry]

  5. I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1958–1966, November 2003.
    [IEEE Xplore entry]

  6. C. A. Zukowski and S.-Y. Wang, “Use of selective precharge for low-power content-addressable memories,” in IEEE International Symposium on Circuits and Systems, vol. 3, 1997, pp. 1788–1791.
    [IEEE Xplore entry]

  7. K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in IEEE Custom Integrated Circuits Conference (CICC), September 2003, pp. 383–386.

  8. F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke and D. E. Somppi, “Fully parallel 30-MHz, 2.5-Mb CAM,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1690–1696, November 1998.
    [IEEE Xplore entry]

  9. H. Zhang, V. George and J. M. Rabaey, “Low-swing on-chip signaling techniques: Effectiveness and robustness,” in IEEE Transactions on VLSI Systems, vol. 8, June 2000, pp. 264–272.
    [IEEE Xplore entry]

  10. Nanosim Reference Guide, Synopsys, March 2002.

  11. I. Y.-L. Hsiao, D.-H. Wang and C.-W. Jen, “Power modeling and low-power design of content addressable memories,” in IEEE International Symposium on Circuits and Systems, vol. 4, 2001, pp. 926–929.
    [IEEE Xplore entry]

  12. J. M. Rabaey, A. Chandrakasan and B. Nikolic Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice- Hall, 2003.

  13. F. Zane, G. Narlikar and A. Basu, “CoolCAMs: Power-efficient TCAM's for forwarding engines,” in IEEE INFOCOM, vol. 1, 2003, pp. 42–52.
    [IEEE Xplore entry]

  14. G. Kasai,Y. Takarabe, K. Furumi and M.Yoneda, “200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,” in IEEE Custom Integrated Circuits Conference, 2003, pp. 387–390.
    [IEEE Xplore entry]