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Paper

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar 2006.
This paper made the Journal of Solid-State Circuits List of Most-Read Articles for the first half of 2006.

Abstract

We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM- design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

List of Citations of This Paper

  1. H. Jang and H.S. Kim, “Hierarchical broadcast ring architecture for high-speed ethernet networks,” IEEE International Conference on Computer Communications (INFOCOMM), Apr 2006, pp. 1–5.

  2. N. Azizi and F.N. Najm, “A family of cells to reduce the soft-error-rate in ternary-CAM,” Design Automation Conference (DAC), Jul 2006, pp. 779–784.

  3. K. Pagiamtzis, N. Azizi and F.N. Najm, “A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme,” IEEE Custom Integrated Circuits Conference (CICC), Sep 2006, pp. 301–372.

  4. A. Agarwal, S.K. Hsu, H. Kaul, M.A. Anders, and R. Krishnamurthy, “A dual-suppy 4GHz 13fJ/bit/search 64x128b CAM in 65nm CMOS,” European Solid-State Circuits Conference, Sep 2006, pp. 303–306.

  5. H. Lu, K. Zheng, B. Liu, X. Zhang, and Y. Liu, “A memory-efficient parallel string matching architecture for high-speed intrusion detection,” IEEE Journal on Selected Areas in Communications, vol. 24, no. 10, pp. 1793–1804, Oct 2006.

  6. A. Mupid, M. Mutyam, N. Vijaykrishnan, Y. Xie, and M.J. Irwin, “Variation analysis of CAM cells,” International Symposium on Quality Electronic Design, Mar 2007, pp. 333–338.

  7. S. Cho, J.R. Martin, R. Xu, M.H. Hammoud, and R. Melhem, “CA-RAM: A high-performance memory substrate for search-intensive applications,” International Symposium on Performance Analysis of Systems and Software, Apr 2007, pp. 333–338.

  8. T. Ramdas, G.K. Egan, D. Abramson, and K. Baldridge, “Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations,” International Conference on Computing Frontiers, May 2007, pp. 267–276.

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  13. E. Anis, N. Nicolici, “On using lossless compression of debug data in embedded logic analysis,” IEEE International Test Conference (ITC), Oct 2007, pp. 1–10.

  14. C-H. Chen, K-S. Hsiao, “Scalable dynamic instruction scheduler through wake-up 1494 locality,” IEEE Transactions on Computers, Nov 2007, pp. 1534–1548.

  15. C. Esteve, F.L. Verdi, M.F. Magalhaes, “Towards a new generation of information-oriented internetworking architectures,” International Conference on Emerging Networking Experiments and Technologies (CoNEXT), 2008.

  16. K. Raghavendra, M. Mutyam, “Process variation aware issue queue design,” Design, Automation and Test, Europe (DATE), Mar 2008, pp. 1438–1443.

  17. S-J. Ruan, C-Y. Wu, J-Y. Hsieh, “Low power design of precomputation-based content-addressable memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Mar 2008, vol. 16, no. 3, pp. 331–335.

  18. W. Xu, T. Zhang, Y. Chen, “Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 1898–1901.

  19. S. Baeg, “Low-power ternary content-addressable memory design using a segmented match line,” IEEE Transactions on Circuits and Systems I: Regular Papers, Jul 2008, vol. 55, no. 6, pp. 1485–1494.

  20. S. Paul, S. Bhunia, “Reconfigurable computing using content addressable memory for improved performance and resource usage,” IEEE/ACM Design Automation Conference (DAC), Jul 2008, pp. 786–791.

  21. Y-J. Chang, Y-H. Liao, “Hybrid-type CAM design for both power and performance efficiency,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Aug 2008, vol. 16, no. 8, pp. 965–974.

  22. X. Liu, X. Yang, Y. Lu, “To filter or to authorize: network-layer DoS defense against multimillion-node botnets,” ACM SIGCOMM Conference on Data communication Applications, Technologies, Architectures, and Protocols for Computer Communication, Aug 2008, pp. 195–206.

  23. O. Tyshchenko, A. Sheikholeslami, “Match sensing using match-line stability in content-addressable memories (CAM),” IEEE Journal of Solid-State Circuits, Sep 2008, vol. 43, no. 9, pp. 1972–1981.

  24. L. Fiorin, G. Palermo, S. Lukovic, V. Catalano, C. Silvano, “Secure memory accesses on networks-on-chip,” IEEE Transactions on Computers, Sep 2008, vol. 57, no. 9, pp. 1216–1229.

  25. S.C. Krishnan, R. Panigrahy, S. Parthasarathy, “Error-correcting codes for ternary content addressable memories”, IEEE Transactions on Computers, Feb 2009, vol. 58, no. 2, pp. 275–279.

  26. V. Uzelac, A. Milenkovic, “A real-time program trace compressor utilizing double move-to-front method”, IEEE/ACM Design Automation Conference (DAC), Jul 2009, pp. 738–743.

  27. S.K. Maurya, L.T. Clark, “Low power fast and dense longest prefix match content addressable memory for IP routers”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Aug 2009, pp. 389–394.

  28. E.A. Daoud, N. Nicolici, “Real-time lossless compression for silicon debug,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep 2009, vol. 28, no. 9, pp. 1387–1400.

  29. M-B. Lin, Y-Y. Chang, “A new architecture of a two-stage lossless data compression and decompression algorithm,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Sep 2009, vol. 17, no. 9, pp. 1297–1303.

  30. W. Jeong, I. Kang, K. Jin, S. Kang, “A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec 2009, vol. 17, no. 12, pp. 1665–1678.

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