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Paper

H. Kimura, K. Pagiamtzis, A. Sheikholeslami and T. Hanyu, “A study of multiple-valued magnetoresistive RAM (MRAM) using binary MTJ devices,” in IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2004, pp. 340–345.

Abstract

This paper presents four-valued magnetoresistive RAM (MRAM) storage cells using one access transistor and two binary magnetic tunnel junction (MTJ) devices with the MTJ devices either in series or in parallel. We present a comparative study of the two cells in terms of their area and power benefits over the binary MRAM, all using the same conventional MRAM process.

List of References

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  2. T. Uemura and M. Yamamoto, “Proposal of four-valued MRAM based on MTJ/RTD structure,” in IEEE International Symposium on Multiple-Valued Logic, 2003, pp. 273–278.

  3. M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, et al., “High-performance MRAM technology with an improved magnetic tunnel junction material,” in IEEE VLSI Technology Symposium, 2002, pp. 212–213.

  4. M. Durlam, P. Naji, A. Omair, M. DeHerrera, et al., “A low power 1Mbit MRAM based on IT1MTJ bit cell integrated with copper interconnects,” in IEEE VLSI Circuits Symposium Digest of Technical Papers, 2002, pp. 158–161.

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