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Paper

K. Pagiamtzis, N. Azizi, F.N. Najm, “A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme,” in IEEE Custom Integrated Circuits Conference (CICC), September 2006, pp. 301–304.

Abstract

Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a binary content-addressable memory (CAM) design with high immunity to SEUs. Conventionally, error-correcting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. The proposed design consists of a new matching technique that uses coding to increase the Hamming distance between words, in conjunction with a modified matchline sensing scheme. The result is a CAM design that reduces the SER with no increase in delay or power dissipation, and with only a 12% increase in area.

List of Citations of This Paper

  1. S.C. Krishnan, R. Panigrahy, S. Parthasarathy, “Error-correcting codes for ternary content addressable memories”, IEEE Transactions on Computers, February 2009, vol. 58, no. 2, pp. 275–279.

  2. A. Bremler-Barr, D. Hay, D. Hendler, and R.M. Roth, “PEDS: A parallel error detection scheme for TCAM devices”, IEEE INFOCOM, April 2009.

  3. S. Yan, Z. Jiaxing, Z. Minxuan, H. Yue, “Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits”, Journal of Semiconductors, February 2010, vol. 31, no. 2.

List of References

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