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Paper

K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in IEEE Custom Integrated Circuits Conference (CICC), September 2003, pp. 383–386.

Abstract

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024 x 144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 μm CMOS process.

List of Citations of This Paper

  1. K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, September 2004.

  2. H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H.J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, “A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture,” in IEEE Solid-State Circuits Conference (ISSCC), February 2004, pp. 208–209, 523.
    [IEEE Xplore entry]

  3. N. Mohan and M. Sachdev, “A static power reduction technique for ternary content addressable memories,” in IEEE Canadian Conference on Electrical and Computer Engineering, May 2004, pp. 711–714, vol. 2.
    [IEEE Xplore entry]

  4. S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, “A dynamic CAM-based on a one-hot-spot block code–for millions-entry lookup,” in IEEE VLSI Circuits Symposium, June 2004, pp. 382–385.
    [IEEE Xplore entry]

  5. H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H.J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “A cost-efficient high-performance dynamic TCAM with pipelined hierarchical search and shift redundancy architecture,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 245–253, January 2005.
    [IEEE Xplore entry]

  6. H. Noda, K. Inoue, H.J. Mattausch, T. Koide, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “Embedded low-power dynamic TCAM architecture with transparently scheduled refresh,” IEICE Transactions on Electronics, vol. E88-C, no. 4, pp. 622–629, April 2005.
    [Oxford Journals Site]

  7. S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, “A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853–861, April 2005.
    [IEEE Xplore entry]

  8. S. Kasnavi, V.C. Gaudet, P. Berube, and J.N. Amaral, “A hardware-based longest prefix matching scheme for TCAMs,” in IEEE International Symposium on Circuits and Systems, May 2005, pp. 3339–3342.
    [IEEE Xplore entry]

  9. S. Kasnavi, P. Berube, V.C. Gaudet, and J.N. Amaral, “A multizone pipelined cache for IP routing,” in IFIP Networking 2005, May 2005, pp. 574–585.

  10. K. Inoue, H. Noda, K. Arimoto, H.J. Mattausch, and T. Koide, “A CAM-based signature-matching co-processor with application-driven power-reduction features,” IEICE Transactions on Electronics, vol. E88-C, no. 6, pp. 1332–1342, June 2005.
    [Oxford Journals Site]

  11. W.A. Vanderbauwhede and D.A. Harle, “Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node,” IEEE Journal of Lightwave Technology, vol. 23, no. 7, pp. 2215–2228, July 2005.
    [IEEE Xplore entry]

  12. D.S. Vijayasarathi, M. Nourani, M.J. Akhbarizadeh, and P.T. Balsara, “Ripple-precharge TCAM: A low-power solution for network search engines,” IEEE International Conference on Computer Design, pp. 243–248, October 2005.
    [IEEE Xplore entry]

  13. G.J. Delgado-Frias, J. Nyathi, and S.B. Tatapudi, “Decoupled dynamic ternary content addressable memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 10, pp. 2139–2147, October 2005.
    [IEEE Xplore entry]

  14. M.J. Akhbarizadeh, M. Nourani, D.S. Vijayasarathi, and P.T. Balsara, “A Nonredundant Ternary CAM Circuit for Network Search Engines,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 3, pp. 268–278, March 2006.
    [IEEE Xplore entry]

  15. K. Pagiamtzis and Ali Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712–727, March 2006.

  16. N. Mohan, W. Fung, D. Wright, and M. Sachdev, “Design techniques and test methodology for low-power TCAMs” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 6, pp. 573–586, June 2006.
  17. M. Nourani, D.S. Vijayasarathi, and P.T. Balsara, “A reconfigurable CAM architecture for network search engines” IEEE Conference on Computer Design, October 2006.

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    [IEEE Xplore entry]

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